George, Tony Gladvin and Malmurugan, N. (2007) The architecture of fast h.264 CAVLC decoder and its FPGA implementation. 2007 THIRD INTERNATIONAL CONFERENCE ON INTELLIGENT INFORMATION HIDING AND MULTIMEDIA SIGNAL PROCESSING, VOL II, PROCEEDINGS. 389-+.
Full text not available from this repository.Abstract
In this paper, we present a fast architecture of real-time CAVLC decoder (CAVLD) implemented in a FPGA. The real-time performance is achieved by exploring the pipelining possibilities between the sub-modules and multi sub-symbol decoding. The implemented fast CAVLD architecture, when integrated with H264 decoder was capable of parsing at 30fps for 1080p streams for an encoded bit stream at a bit rate of 200 Mbps to achieve the real-time performance, while the clock is operated at 74.25 MHz. The result numbers of ALUs are 3266 and the critical path is within 10.5ns
| Item Type: | Article |
|---|---|
| Depositing User: | Unnamed user with email techsupport@mosys.org |
| Last Modified: | 06 Feb 2026 06:51 |
| URI: | https://ir.vmrfdu.edu.in/id/eprint/6152 |
Actions (login required)
- View Item