Interleaving with error correction coding effectively combats burst errors in digital communication. This work presents a reconfigurable interleaver architecture for the turbo decoder in 3GPP systems. Conventional interleaver designs consume significant silicon area. The proposed architecture uses algorithmic simplifications to achieve low-cost implementation and reduces FPGA resource consumption substantially, requiring only 4856 logic elements. © 2006-2014 CCC Publications. © 2018 Elsevier B.V., All rights reserved.